x86 32bit Processor Core
6 stage pipe-line
Floating point unit support
Extends CPU instruction set to include Trigonometric, Logarithmic and Exponential
Implements ANSI/IEEE standard 754-1985 for binary Floating-Point Architecture
Embedded I/D Separated L1 Cache
16K I-Cache, 16K D-Cache
Embedded L2 Cache
4-wary 256KB L2 Cache
Write through or write back policy
DDRII Control Interface
6 bits data bus
DDRII clock support up to 200MHz
DDRII size support up to 1GB
IDE Controller
Support 2 channels Ultra-DMA 100 (Disk x 4)
Primary channel support SD card
LPC (Low Pin Count) Bus Interface
GPU Control Unit
VGA controller
2D Graphics engine support
MAC Controller x 1
PCI Control Interface
Up to 3 sets PCI master device
3.3V I/O
ISA Bus Interface
AT clock programmable
8/16 Bit ISA device with Zero-Wait-State
Generate refresh signals to ISA interface during DRAM refresh cycle
HDA Controller
DMA Controller
Interrupt Controller
2 sets of 8254 timer controller
Timer output is 5V tolerance I/O on 2nd Timer
Real Time Clock (Internal Mode or External Mode)
Less than 2uA (3.0V) power consumption in Internal RTC Mode while chip is power-off
FIFO UART Port x 3 (3 sets COM Port)
Compatible with 16C550/ 16C552
Default internal pull-up
Supports the programmable baud rate generator with the data rate from 50 to 115.2Kbps
Programmable character options
Support TXD_En Signal on COM1/COM2
Port 80h output data could be sent to COM1 by software programming

 Parallel Port

Support SPP/EPP/ECP mod

General Programmable I/O

Supports 40 dedicated programmable I/O pins
Each GPIO pin can be individually configured to be an input/output pin
GPIO_P0~GPIO_P3 can be programmed by 8051
GPIO_P0 and GPIO_P1 with interrupt support (input/output)

USB 2.0 Host Support

Supports HS, FS and LS
4 ports

USB 1.1 Host Support

Supports FS with 3 programmable endpoint
1 port

PS/2 Keyboard and Mouse Interface Support

Compatible with 8042 controller

Redundant System Support

Speaker out

Embedded 2MB Flash

For BIOS storage

I²C bus x 2

Compliant with V2.1
Some master code (general call, START and CBUS) not support

Servo Control interface support

General Shift interface support

JTAG Interface supported for S.W.


Input clock


Output clock

24 MHz
25 MHz
PCI clock
DDRII clock

Operating Voltage Range

Core voltage: 1.0 V ± 5%
I/O voltage: 1.8V ± 5% , 3.3 V ± 10 %

Operating temperature

0 ~ 70°C

Package Type

31x31mm, 720 Ball BGA




Block Diagram