x86 Processor Dual Core

Symetric Multi-Processors
6 stage pipeline
X86 instruction set

Floating point unit support

Extends CPU instruction set to include Trigonometric, Logarithmic and Exponential
Implements ANSI/IEEE standard 754-1985 for binary Floating-Point Architecture

Embedded I / D Separated L1 Cache

8-way 32K I-Cache, 8-way 32K D-Cache

Embedded Unified L2 Cache

4-way 512KB L2 Cache
Write through or write back policy

System DDR3 Control Interface

32-bit data bus
DDR3 size support up to 2Gbytes

GPU Control Unit

UMA architecture
VGA controller
2D Graphics engine support
Max display resolution 1920×1440@60Hz with 234MHz video clock
Dual Display support:, only one display can be 1920×1200, 1 DVO (24bits) & 1 D-SUB or 2 DVO (12bit x 2)
Support H.264 1080P video decode

Temperature sensor

MAC Controller x 1

Embedded 2MB Flash

For BIOS storage

JTAG Interface supported for S.W. debugging

IDE Controller

PATA 100(HDD x 2) or SD x 2 at Primary Channel

SATA 1.5Gb/s (1 Port) at Secondary Channel

PCIE Control Interface x 2

Up to 2 sets PCIE device
3.3V I / O

USB 2.0 Host Support

Supports HS, FS and LS
4 port

HDA Controller

ISA Bus Interface

AT clock programmable
8/16 Bit ISA device with Zero-Wait-State

DMA Controller

8259 Interrupt Controller

Counter / Timers

2 sets of 8254 timer controller
Timer output is 5V tolerance I/O on 2nd Timer

Real Time Clock

Less than 2.5uA (3.0V) power consumption in Internal RTC Mode while chip is power-off.

FIFO UART Port x 9 ( 9 sets COM Port )

Parallel Port x 1

General Programmable I/O

I2C bus x 2

MTBF Counter

ADC Interface x 8

General Shift Interface Support

Full Duplex SPI bus x 2

Input clock

25 MHz , 14.318MHz

Output clock

DDR3 clock

Operating Voltage Range

Core voltage: 0.9V± 5%
I / O voltage: 1.2V ± 5%, 1.5V ± 5%, 1.8V ± 5%, 3.3 V ± 10 %

Operating Temperature

-40℃ ~ 85℃

Package Type

31x31mm, 720 Ball PBGA



Block Diagram